“Delivering a total bandwidth of up to 1.6Tbit/s, the enables up to 16 lanes of multi-standard PHY supporting PCIe 6.0, CXL 3.x and 800G Ethernet in a combination of mixed operating modes,” according to the company.
“Our hyperscaler and datacenter infrastructure customers can mix and match custom SoCs with our I/O connectivity or memory expansion chiplets, providing flexibility and scalability for their systems,” said Alphawave general manager Mohit Gupta.
The 24Gbps UCIe silicon platform was unveiled at the 2024 Chiplet Summit in Santa Clara.
